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An Introduction to Power MOSFET and SJ Power MOSFET


MOSFET is a basic element of integrated circuit. Its circuit symbols and device structures are shown in Figure 1. The typical N-channel MOS device has 4 electrodes, and is connected with different voltage bias. In general, the source and substrate electrodes are connected to a low potential, such as the ground. When the device is not working, the device is in a cut-off state, and there is no conductive channel between the source and the drain of the device, which is equivalent to the disconnection state of the switch. When the gate is coupled with a positive voltage of larger than Vgs (th), the surface of the P substrate below the gate oxide will generate an inversion layer, which is a conductive channel. The channel is connected with the source and drain of the device, and the nMOS is in the state of conduction at this time. The higher the gate voltage, the better the conduction.


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    Fig1 MOSFETbasic structure                    Fig2 VDMOS structure



In the middle and high voltage power MOSFET, the vertical channel structure is usually adopted, as shown in Figure 2, the drain of the device is in the bottom of the chip, the source is at the top of the chip, and the whole device is placed in a vertical structure. This structure is called Double-diffusion MOS Vertical (VDMOS). From the structure, the drain of the VDMOS is moved from the original surface position to the bottom of the device, and the drain current is corresponding to the surface of the device from the bottom of the device to the device. The area between the drain current and the channel is the drift region, which is the main part of the high voltage power device. The thicker the drift region and the lower the resistivity of the drift region, the higher the voltage is, and the higher the resistance of the device at the same time. This is because the Rdson VDMOS 2~2.5 and BVdss is proportional to the square as shown by Formula:


Rdson = a* BV2~2.5


The use of super-junction MOSFET can break this limit, the basic structure as shown in figure 3. The biggest difference from VDMOS is that a P pillar is added to the bottom of the pbody, which creates a drift region with P/N balanced. By using the principle of mutual depletion between adjacent PN columns, the concentration of the drift region can be promoted, and the resistivity of the device is reduced. While in the off state, between the P and N columns can be mutual depletion, the depletion region is expanded to endure the high electric field, thus breaking the silicon limits, the turn-on resistance and breakdown voltage is reached an approximate linear relationship, significantly improve the device performance.


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Fig3 SJ VDMOS illustration


Compared to common VDMOS devices, the super junction power device is faster, Lower FOM, but it will also bring some other negative issues, such as high di/dt; dv/dt, gate oscillation and EMI problem. Therefore, the design of the device is very important to improve the EMI.


GreenMOSTM Introduction

GreenMOS series of products is the new generation of super junction power devices. The word of "green" means that GreenMOS itself is a high quality "green" product, using GreenMOS can achieve green design and obtain green energy products. GreenMOS series products covers voltage range of 500~800V, a minimum of 1A to maximum 76A.  A total of nearly a hundred part numbers of different types of package and chip specifications. Due to the adoption of the Oriental Semiconductor's multiple patented technologies, GreenMOS series of products successfully overcome the EMI issue of conventional super junction products. Its performance reached or even exceeded the level of the international first-tier brand. Compared with other company's super junction devices, GreenMOS has the advantage of "fast but not oscillated":


1.   Soft Switching

Multiple optimization has been implemented on GreenMOS manufacturing processes, the devices performance is more suitable for the fast switching, reduces the noise and ripple voltage spikes and the switching waveform is smoother to improve system EMI.



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Fig4. Conventional SJMOSv.s. GreenMOS switching waveform


2.   LOW FOM


FOM (Figure of Merit) is an important standard to measure the power device design, the calculation formula for the Rdson*Qg, the smaller the better performance of the device. After optimization of the manufacturing process of devices, GreenMOS achieves very low Qg, as well as superior on state resistance. These two advantages enable GreenMOS to achieve industry's leading FOM value, so that the dynamic loss of GreenMOS can be reduced to the 2/3 of the conventional super junction devices. It also supports up to 2MHz switching frequency. The switching speed is close to the next generation semiconductor devices - high voltage GaN power devices.



Fig5. GreenMOSTM 2MHz switching waveform



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